Ex parte Keller
Appeal 2009009225, Appl. No. 11/176,819, Tech. Center 2100
Decided June 15, 2010
The claims on appeal related to a memory controller in a computer. Dependent claim 5 was rejected as obvious, and the feature argued by the Applicant related to selective interleaving: "wherein said method further comprises selectively only interleaving storage of consecutive memory chunks across said multiple sets of said physical dynamic memory devices within said first portion of said memory array,"
The Examiner rejected the parent independent claim using a combination of two references, and added a third reference (Roy) to reject dependent claim 5. As a motivation to combine Roy's interleaving technique with the other two references, the Examiner offered:
Roy teaches performance improvement techniques such as interleaving can reduce the memory system bus cycle time by up to half that of any of the DRAMs individually.
The Board first found that the combination did not disclose selective interleaving as described in claim 5. Roy disclosed the existence of two types of computer systems: those that interleave memory and those don't interleave memory. However, the Board found that this did not amount to a teaching of a system that selectively interleaved some chunks of memory while not interleaving other chunks of memory.
The Board went further to reject the Examiner's motivation to combine, finding that the teaching used by the Examiner as a motivation to add Roy to the combination did not relate to the feature used in the combination – selective interleaving. The benefit of reduced cycle time related instead to a different feature – increasing width of the data bus.
The Board found the Examiner's motivation to combine deficient in yet another way: solving the problem noted in the reference simply didn't suggest the claimed feature of selective interleaving:
Even if this disclosure related to the interleaving memory technique, recognizing problems with interleaving memory would not have taught or suggested combining interleaving and non-interleaving using a single memory array.
My two cents: The rationale used by the Examiner for the combination – improved performance – is an example of what I call a "generic rationale". This decision shows one of two ways I know to fight a generic rationale: argue that the Examiner hasn't shown that the combination actually provides the benefit. The second is to argue that the alleged benefit isn't really beneficial at all or is outweighed by drawbacks.
What initially drew my attention to this decision was the Examiner's mistake in relying on an advantage that wasn't related to the claimed feature. However, the Board's initial finding that the combination did not teach all the elements contained a useful nugget also.
Specifically, a reference that discloses the presence of a particular feature in one embodiment along with the absence of the same feature in another embodiment does not teach selectively enabling the feature. I've seen this sort of rejection before, and I'm glad to to see the Board is persuaded by this reasoning.
Related posts: Ex parte Khayrallah, which I discussed here, makes the point that disclosure of two options for building a system is not selective disablement of options during system operation. Ex parte Rykowski, which I discussed here, is another example of a successful attack on a generic rationale.