Takeaway: In Ex parte Fujimori, BPAI affirmed an obviousness rejection of a claim to a single chip supporting multiple wired Ethernet physical protocol sub-layers. No interaction between the protocol sub-layers was claimed. The Applicant argued that the primary wired Ethernet reference could not be combined with the secondary wireless Ethernet reference without changing the principle of operation of the primary reference. The Board disagreed, nothing that obviousness does not require the bodily incorporation of one reference into another. The Board concluded the claimed combination is "a simple arrangement of old elements, with each performing the same function it had been known to perform, yielding no more than one would expect from such an arrangement."
Details:
Ex parte Fujimori
Appeal 2009007214; Appl. No. 10/282,933; Tech. Center 2400
Decided February 28, 2011
The technology in the application on appeal involved a physical layer integrated circuit for high speed wired Ethernet. A representative claim on appeal read:
1. A single-chip multi-sublayer PHY to support 10 Gigabit digital serial communications, said single-chip comprising:
a PMD transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation, 10 Gigabit Fibre Channel operation, and signal equalization;
a PMD PCS CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation;
a XGXS PCS CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation; and
a XAUI transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation.
(Emphasis added.)
The Examiner rejected the originally filed claims – which did not include the "signal equalization" limitation – as obvious over Applicant admitted prior art in view of a 10 Gigabit Ethernet whitepaper. According to the Examiner, the Background section of Applicant's specification taught everything but Fibre Channel operation. The Applicant argued that the references did not teach that the claimed functionalities were present in a CMOS sublayer.
The Examiner withdrew the obviousness rejection and rejected as anticipated by a integrated circuit datasheet published by Mindspeed. The Applicant amended to distinguish, by adding the "signal equalization" limitation to the PMD transmit/receive CMOS sublayer.
The Examiner changed the obviousness rejection to use a different secondary reference. The Mindspeed publication used as a primary reference disclosed an Ethernet transceiver having the three (protocol) sublayers, and all the claimed functionality except for signal equalization in the PMD tx/rx CMOS sublayer. As the new secondary reference, the Examiner used a reference teaching signal equalization in a PMD sublayer.
The Applicant argued that the secondary reference taught signal equalization in a different layer (XAUI tx/rx) than claimed (PMD tx/rx). The Applicant went on to argue:
In fact, Shi does not disclose or suggest any PMD sublayer characteristics or functionalities whatsoever. ... Therefore, the proposed combination of Mindspeed and Shi does not teach or suggest "a PMD transmit/receive CMSO sublayer supporting at least 10 Gigabit Ethernet operation, 10 Gigibit Fibre Channel operation, and signal equalization," such as recited in claim 1.
The Examiner switched the secondary reference again, to a draft proposal for a new Ethernet standard. The Applicant argued that the secondary reference was directed to a wireless protocol (802.16 or WiMAX), where 10 Gigabit Ethernet was a wired protocol. "Therefore, the electrical and protocol characteristics of the PHYs for the 10 Gigabit Ethernet protocol and the IEEE 802.16 protocol are completely different.
The Examiner maintained the rejection, and Applicant went to appeal. In the Appeal Brief, the Applicant argued:
Since Hunter relates to a wireless protocol and 10 Gigabit Ethernet relates to a wired protocol, Hunter does not (and cannot) disclose "a single-chip multi-sublaver PHY to support 10 Gigabit digital serial communications, said single-chip comprising a PMD transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation . . . and signal equalization," as recited by Applicant's claim 1 (emphasis added).
Hunter cannot modify Mindspeed because Mindspeed relates to a wired protocol and Hunter relates to a wireless protocol with different electrical and protocol characteristics of the PHY. Any changes to Mindspeed using the teachings of Hunter will change the principal of operation of Mindspeed since Mindspeed and Hunter teach different PHY protocol characteristics.
The Board said the Applicant went wrong in assuming that the combination involved literally ("bodily") incorporating the wireless chip into the wired chip.
That is, the test for obviousness is not whether Hunter can be bodily incorporated into the structure of Mindspeed, but rather it would have been obvious to combine Hunter’s teachings that a PMD sublayer can be used to support signal equalization to the teachings of Mindspeed’s PMD sublayer that supports signal conditioning. ... [W]e conclude that such combination is no more than a simple arrangement of old elements, with each performing the same function it had been known to perform, yielding no more than one would expect from such an arrangement. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The skilled artisan would “be able to fit the teachings of multiple patents together like pieces of a puzzle” since the skilled artisan is “a person of ordinary creativity, not an automaton.” Id. at 420-21. Appellants have presented no evidence that supporting signal equalization (as discussed by Hunter) as Mindspeed’s signal conditioning was “uniquely challenging or difficult for one of ordinary skill in the art” or “represented an unobvious step over the prior art.” See Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 418-19).
My two cents: The lesson here: a claim to a combination of known elements is prima facie obvious over a combination of references that does not teach how to accommodate technical differences between the elements, as long as the claim doesn't capture how the differences are handled either. Here, even if there were differences in the "electrical and protocol characteristics" of Gigabit Ethernet's physical layer WiMAX's physical layer, so what? Nothing about electrical or protocol characteristics was expressed in the claims.
So if there is some technical magic involved to bridge the differences, put that magic in the claims. Otherwise, the PTO will assume that you did nothing more than place three existing protocol sublayers on the same chip.
"a claim to a combination of known elements is prima facie obvious over a combination of references that does not teach how to accommodate technical differences between the elements, as long as the claim doesn't capture how the differences are handled either"
ReplyDeleteick .... I wouldn't talk to clients with that mouth. I enjoy many of your posts Karen, but I would have never written what you just did.
It is readily apparent that you read a lot of BPAI cases, so why haven't you realized that like the Federal Circuit, whether you win or lose at the BPAI is oftentimes a reflection of the panel you get (and their predisposition towards the invention) and not your arguments.
Just because one panel looking at one particular set of facts makes some pronouncement does not mean (in the slightest) that every panel with a similar set of facts is going to hold the same way.
Again, I enjoy what you do but please try to stay away from the sweeping generalizations based upon a very limited data set.
My opinion is that the argument needs to be more compelling. You can overcome the obviousness rejection if you focus on the re-arrangement being more than "simple re-arrangement of old elements."
ReplyDeleteIn other words, their argument "Any changes to Mindspeed using the teachings of Hunter will change the principal of operation of Mindspeed since Mindspeed and Hunter teach different PHY protocol characteristics" needed to say that using different protocol characteristics would be difficult, and therefore non-obvious. Would help to file a declaration to that effect too.
My two cents is that the basis of their argument isn't an automatic loser; the argument just needed to be developed much more thoroughly.
This is actually a pretty old argument and one that pops up quite often. Oftentimes I go ahead and give it to the applicant simply because I'm persuaded (generally more by myself than by the applicant) that the combination simply wouldn't have been "lying in the middle of the road of technical progress" so to speak, based upon the references I'm looking at.
ReplyDeleteFact is, when I'm formulating a rejection on nonfinal, once I've got something that looks passable or rock solid by the time I'm done writing it up I'm less convinced than I was at the outset of writing the rejection itself. Nevertheless, by the time it is written it is all but set in stone, the decision to reject generally comes before I write it down, writing it down is simply me providing notice to the applicant for the grounds. I would have to see some major problem with the rejection to not send it once it is written. Perhaps that is in error or perhaps that is not a best practice but that's how the ball bounces, especially if there are many possible rejections to make.
But in any event, yeah, this kind of case can go both ways and it would be nice to have more fed. circ. opinions on point directly on this topic doing a comprehensive view of the lawl and a whole hearted joining in of all the panel members or perhaps the en banc bunch.
Anonymous 10:55 said
ReplyDelete>whether you win or lose at the BPAI is
>oftentimes a reflection of the panel you get
Absolutely. I'd say this is true more so at the BPAI than at the Fed Cir, simply because there are so many more ALJs.
>sweeping generalizations based upon a very
>limited data set.
None of my posts involve any sort of statistical analysis. I simply read a lot and use that to inform what I write about. So all my posts are vulnerable to this criticism. I can live with that.
I find that the type of obviousness rejection seen in Fujimori is upheld a lot. I didn't write this post solely based on this one case.
I wrote about this case because it struck me as a egregious example of a "simple arrangement of old elements, with each performing the same function it had been known to perform, yielding no more than one would expect from such an arrangement."
I think my two cents was a decent paraphrase of KSR's warning against "simple arrangements." I'm surprised you find my two cents so objectionable. If your claim combines known elements without including the technical differences, how do you expect to avoid an obviousness rejection, even one based on high level references that don't include technical details?
Anonymous 1:15 said;
ReplyDelete>But in any event, yeah, this kind of case can
>go both ways
I'm sure you could tell from my post that I don't see this one as being on the fence.
I'm curious to know what sort of NON-obviousness you see here, based on the record.
WindyCity said:
ReplyDelete>[stronger argument would] say that using
>different protocol characteristics would be
>difficult, and therefore non-obvious.
Agreed. Not just *say* but really explain why.
>Would help to file a declaration to that
>effect too.
I think in a case like this you'd almost certainly need declaration evidence to persuade the Board.
I say that because I saw nothing in the spec that said "here's why it was really hard and here's the magic we used to accomplish this." And the farther you stray from the spec, the more likely it is that the BPAI will say "attorney argument is not evidence."
[Though I'm not a EE, so some might say I'm not qualified to interpret the spec or the art in this "EE case". Note that this "EE case" contained a bunch of diagrams with functional blocks like "serializer" and "sync detect."]
"I'm sure you could tell from my post that I don't see this one as being on the fence.
ReplyDeleteI'm curious to know what sort of NON-obviousness you see here, based on the record."
To be sure, in this case I'm not 100% sure. First because the terminology they're using is probably passe nonsense. Supposedly what is being claimed is a PHY. In other words, a "physical layer" in the abstract. Supposedly it is being implemented in a single chip but nevertheless, what is claimed is the PHY itself. Supposedly the chip itself comprises a few "sublayers" (in the abstract, not a real tangible layer) which are implemented in turn in CMOS see:
"a PMD transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation, 10 Gigabit Fibre Channel operation, and signal equalization;
a PMD PCS CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation;
a XGXS PCS CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation; and
a XAUI transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation.
(Emphasis added.)"
To be clear, they're lucky they even got to the prior art. I give them a 112 enablement rejection stating that chips do not comprise "sublayers" in the abstract and it is fundamentally impossible to make a chip thus as chips are not made out of abstractions.
Then I probably reject under 35 USC 101 for attempting to claim the abstract idea of these "sublayerslol".
Then I write whatever bs 102/103 I possibly might desire, because this case is on a one way track to nowhere just like the other few cases I have that are claimed in similar bs fashion.
But as to it being "non-obvious" I'm not even sure, I have a really hard time doing an obviousness analysis on things that don't actually exist and are only abstract concepts. I might even refuse to do one in a case like this.
And note, before your brain explodes, that "supporting ... blah blah blah" are not "functional" limitations. They're method step limitations. It is what is happening supposedly RIGHT NOW, not what the device or sub component DOES.
"I'm sure you could tell from my post that I don't see this one as being on the fence.
ReplyDeleteI'm curious to know what sort of NON-obviousness you see here, based on the record."
To be sure, in this case I'm not 100% sure. First because the terminology they're using is probably passe nonsense. Supposedly what is being claimed is a PHY. In other words, a "physical layer" in the abstract. Supposedly it is being implemented in a single chip but nevertheless, what is claimed is the PHY itself. Supposedly the chip itself comprises a few "sublayers" (in the abstract, not a real tangible layer) which are implemented in turn in CMOS see:
"a PMD transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation, 10 Gigabit Fibre Channel operation, and signal equalization;
a PMD PCS CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation;
a XGXS PCS CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation; and
a XAUI transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation.
(Emphasis added.)"
To be clear, they're lucky they even got to the prior art. I give them a 112 enablement rejection stating that chips do not comprise "sublayers" in the abstract and it is fundamentally impossible to make a chip thus as chips are not made out of abstractions.
Then I probably reject under 35 USC 101 for attempting to claim the abstract idea of these "sublayerslol".
Then I write whatever bs 102/103 I possibly might desire, because this case is on a one way track to nowhere just like the other few cases I have that are claimed in similar bs fashion.
But as to it being "non-obvious" I'm not even sure, I have a really hard time doing an obviousness analysis on things that don't actually exist and are only abstract concepts. I might even refuse to do one in a case like this.
And note, before your brain explodes, that "supporting ... blah blah blah" are not "functional" limitations. They're method step limitations. It is what is happening supposedly RIGHT NOW, not what the device or sub component DOES.
"And note, before your brain explodes, that 'supporting ... blah blah blah' are not 'functional' limitations."
ReplyDeleteYes they are. As a personal preference, I would use the phrase "configured to ...", but there is nothing wrong with supporting. As an Examiner, you should spend more time addressing the actual limitations than trying to find a way to ignore them. Properly presented, there is just too much Federal Circuit case law that essentially says "the examiner cannot ignore limitations" for you to try playing those games.
Like with anything, if you don't properly raise this case law before the BPAI, then the examiner might win on that point. Regardless, I've always found that a sure sign of a lazy/incompetent examiner is when they try to ignore your limitations rather than address them head on -- these are easy cases to take to the BPAI.
"Properly presented, there is just too much Federal Circuit case law that essentially says "the examiner cannot ignore limitations" for you to try playing those games."
ReplyDeleteAs I thought I've made crystal clear over the years, I would not ignore them. Maybe you're new here. I would stick you with an additional 112 2nd and 101 for mixing your statutory categories. And trust me, I would not be "trying" anything. I'd be "doing" something. Rejecting your claims. Which happens to be something I do a lot.
Regardless, they're not getting over an enablement rejection in this particular case anytime soon so the functional/method step debate will be taking a backseat to that.
>Supposedly what is being claimed is a PHY.
ReplyDelete>In other words, a "physical layer" in the
>abstract.
The plain language of the claim says a chip, ie, a piece of silicon. That's not abstract. It certainly can't be construed as "software".
>Supposedly it is being implemented in a
>single chip but nevertheless, what is
>claimed is the PHY itself.
I say a POSITA interprets this claim as a chip implementing an Ethernet physical layer. If it were my case, I'd consider offering evidence to support my interpretation.
>Supposedly the chip itself comprises a few
>"sublayers" (in the abstract, not a real
>tangible layer)
Right: not claiming a physical layer of the silicon. Claiming a chip implementing four protocol sublayers defined by the Ethernet standard.
>which are implemented in turn in CMOS
Implemented. Instantiated. Real. Not abstract.
>112 enablement rejection stating that
>chips do not comprise "sublayers" in the
>abstract and it is fundamentally impossible
>to make a chip thus as chips are not made
>out of abstractions.
Ah, an enablement rejection. Creative. But it's only impossible to make/use the claim because your claim construction is unreasonably broad. A reasonable claim construction as understood by a POSITA, is that what's claimed is a real, physical piece of silicon having specific functionality.
> "supporting ... blah blah blah" are not
>"functional" limitations. They're method
>step limitations.
So is your claim interpretation -- and thus your enablement rejection and your objection to its abstractness -- based on this?
I wouldn't have a problem changing the claim language to make it a functional limitation. My personal choice would be "logic configured to". Makes perfect sense in this case. We're talking about a silicon implementation. Really does use logic. The logic gates really are configured in a certain way (arranged physically) to perform a certain function.
>But as to it being "non-obvious" I'm not even
ReplyDelete>sure, I have a really hard time doing an
>obviousness analysis on things that don't
>actually exist and are only abstract
>concepts. I might even refuse to do one in
>a case like this.
Does the MPEP say you can do this?
Certainly, as an Examiner, you *can* refuse to do prior art examination on a claim that feels abstract to you. All the applicant can do in response is a) Examiner interview; b) talk to your SPE and c) petition. IOW, not much.
Why is it you have a hard time doing obviousness analysis on this claim? I find it hard to believe that you can't imagine an alternative claim construction in which the chip is physical rather than abstract.
I noted that you started to realize what was up approximately at the end of your response Karen, but had already started my response.
ReplyDelete"I say a POSITA interprets this claim as a chip implementing an Ethernet physical layer. If it were my case, I'd consider offering evidence to support my interpretation. "
I say that if you want a POSITA to interpret your claim as a chip which happens to be implementing an "Ethernet physical layer" in the abstract then you can claim that and we'll let my good buddy 112 1st para WD sort out whether or not you can. Until then you can have a Miyazaki 112 2nd in response to your arguments and evidence complete with a correct interpretation of the claim. Along with a 112 2nd failure to claim what the applicant subjectively believes to be his invention as evidenced by his attorney's arguments.
"Right: not claiming a physical layer of the silicon. Claiming a chip implementing four protocol sublayers defined by the Ethernet standard. "
Mhmmm, in other words, your claim is 101 fried. Chips "implementing" the four abstract protocol sublayers defined by the Ethernet standard is claiming every use of the overall abstract idea of those protocol layers so far as I'm aware. 1 0 1. Not to even mention that chips do not "comprise" abstractions which is precisely what those layers are. As I mentioned. 112 enablement.
"Implemented. Instantiated. Real. Not abstract. "
You're welcome to make that argument and when you find out that it is irrelevant to the 101 inquiry call me. Because I want to lol. In your face. The question, Karen, is whether or not an abstract idea is preempt. The answer as of this moment appears to be yes. They specifically drafted the claims to do such. Ok? They specifically intend for it to. They have gone out of their way to ensure that it will because that is where the value is. All that remains to do is write down the abstract idea that is being preempt and frankly I'm too lazy to do it for you, you readers need exercise.
"But it's only impossible to make/use the claim because your claim construction is unreasonably broad. "
Not at all. I limited the claim to precisely what they want the claim to be limited to. And how are we going to know? Because they're going to respond and probably put a little of their claim construction on the record and it isn't going to jive with their language in the current claim. That is, it is going to be substantially different than what is claimed. Then we're going to give them a 112 2nd failure to claim what they subjectively believe to be their invention. When they eventually put down what they wanted to claim, which they invariably will, my friend 112 1st para WD is probably going to want to have a discussion with them.
"A reasonable claim construction as understood by a POSITA, is that what's claimed is a real, physical piece of silicon having specific functionality."
Pieces of silicon do not have specific functionalities. They just kind of sit there.
http://en.wikipedia.org/wiki/Boule_(crystal)
Specific devices made in/with silicon have functionalities. We however do not have specific devices here. We have abstract ideas supposedly implemented in an abstraction of a class of devices known generically as CMOS technology (analogous to a general purpose computer). There is a difference.
I noted that you started to realize what was up approximately at the end of your response Karen, but had already started my response.
ReplyDelete"I say a POSITA interprets this claim as a chip implementing an Ethernet physical layer. If it were my case, I'd consider offering evidence to support my interpretation. "
I say that if you want a POSITA to interpret your claim as a chip which happens to be implementing an "Ethernet physical layer" in the abstract then you can claim that and we'll let my good buddy 112 1st para WD sort out whether or not you can. Until then you can have a Miyazaki 112 2nd in response to your arguments and evidence complete with a correct interpretation of the claim. Along with a 112 2nd failure to claim what the applicant subjectively believes to be his invention as evidenced by his attorney's arguments.
"Right: not claiming a physical layer of the silicon. Claiming a chip implementing four protocol sublayers defined by the Ethernet standard. "
Mhmmm, in other words, your claim is 101 fried. Chips "implementing" the four abstract protocol sublayers defined by the Ethernet standard is claiming every use of the overall abstract idea of those protocol layers so far as I'm aware along with a field of use limitation involving it having been implemented in "CMOS" used here to merely refer to the technology rather than any specific arrangement of MOS transistors. 1 0 1. Not to even mention that chips do not "comprise" abstractions which is precisely what those layers are. As I mentioned. 112 enablement.
"Implemented. Instantiated. Real. Not abstract. "
ReplyDeleteYou're welcome to make that argument and when you find out that it is irrelevant to the 101 inquiry call me. Because I want to lol. In your face. The question, Karen, is whether or not an abstract idea is preempt. The answer as of this moment appears to be yes. They specifically drafted the claims to do such. Ok? They specifically intend for it to. They have gone out of their way to ensure that it will because that is where the value is. All that remains to do is write down the abstract idea that is being preempt and frankly I'm too lazy to do it for you, you readers need exercise.
"But it's only impossible to make/use the claim because your claim construction is unreasonably broad. "
Not at all. I limited the claim to precisely what they want the claim to be limited to. And how are we going to know? Because they're going to respond and probably put a little of their claim construction on the record and it isn't going to ji ve with their language in the current claim. That is, it is going to be substantially different than what is claimed. Then we're going to give them a 112 2nd failure to claim what they subjectively believe to be their invention. When they eventually put down what they wanted to claim, which they invariably will, my friend 112 1st para WD is probably going to want to have a discussion with them.
"A reasonable claim construction as understood by a POSITA, is that what's claimed is a real, physical piece of silicon having specific functionality."
ReplyDeletePieces of silicon do not have specific functionalities. They just kind of sit there.
http://en.wikipedia.org/wiki/Boule_(crystal)
Specific devices made in/with silicon have functionalities. We however do not have specific devices here. We have abstract ideas supposedly implemented in an abstraction of a class of devices known generically as CMOS technology (analogous to a general purpose computer). There is a difference.
"So is your claim interpretation -- and thus your enablement rejection and your objection to its abstractness -- based on this? "
ReplyDeleteNope, my claim interpretation and thus my enablement rejection are based on the claim and the spec. Your failure at the outset to properly construe the claim and thus understand the rejections is your business. I note that this is just one claim construction issue I took the time to point out specifically but there are probably at least another three things you're misinterpreting in this claim because you don't know wtf is going on in the technology. Which is fine, because you're not the attorney of record. What isn't fine is that the attorney of record is similarly disadvantaged.
"I wouldn't have a problem changing the claim language to make it a functional limitation."
You don't think you'd have a problem. And more power to you to make such an amendment. That is, if you have WD support, and it doesn't look like they do. But they're welcome to try. The more they amend the more they get closer to what they meant to claim and the closer they get to making my 101 stick to them more and more.
This has already played out several times irl Karen it isn't my first rodeo. Cases like this end in tear-eyed applicants when it comes before me. And they have you "softywofties" as malcolm likes to call you, to thank for it.
"My personal choice would be "logic configured to"."
Well you'd be making the predictable progress. I'm still 2 steps (or more) ahead of you though.
But in any case will that be your personal choice ivo the originally filed app? Mhmmm. Doubt it. I note you changed over from your previous position of this being merely a "piece of silicon" or whatever to it now magically comprising "logic". That is quite a leap sister. Which is it going to be?
Oh Karen, it would be fun to play with you irl. Oh how you'd squirm before your client struck the killing blow.
And btw, just when you think you might get through with the substance you can also deal with an objection to the drawings for not having shown me this supposed certain configuration that does these things.
See Karen, in the arts where you can't rely on bsing we have tools to make you do our bidding. This is why people take offense to the special treatment given to softwaretards.