Ex parte Henderson
Appeal 2009004652; Appl. 10/405,904; Tech. Center 2600
Decided: May 17, 2010
The patent application on appeal involved image arrays such as those used in digital cameras. A representative claim on appeal read:
10. An image array sensor comprising:
an array of pixels arranged in rows and columns, each pixel comprising a light-sensitive element and switching means for applying a reset signal to the pixel and to read out a pixel signal from the pixel;
a dual mode common integrated read-reset circuit, in each column, to operate as a buffer in a first mode to apply the reset signal to the pixels, and to also operate as a comparator in a second mode to read pixel reset signals and pixel signals;
analog-to-digital conversion means for converting the pixel reset signals and the pixel signals from analog to digital; and
a memory to store the digital pixel reset signals of the pixels for up to a complete frame.
The Applicant added the phrase "dual mode common integrated" during prosecution to distinguish over a § 102 reference. The Applicant explained the difference as follows:
Although Applicant maintains that Boemler et al. does not disclose a read-reset circuit operating in two modes, to further advanced prosecution Applicant has amended independent Claim 10, 17, and 24 to recite a dual mode common integrated reset circuit, in each column .... Boemler et al. discloses a separate amplifier and comparator for each column of pixels and not a dual mode common integrated read-reset circuit ....
The next Office Action converted the anticipation rejection to an obviousness rejection by adding a secondary reference for teaching a "common integrated circuit." The Examiner also noted that "the new limitation of dual mode does not further limit the claim since there were already two modes claimed." The Examiner also rejected the amended claims under § 112 First, Written Description, explaining that:
The limitation of an integrated circuit was not disclosed in the specification. While different circuits are described, none of them are referenced to as an integrated circuit.
In response to the Written Description rejection, the Applicant argued that the limitation was described in Figures 1 and 2 and specific passages in the specification. The Applicant argued obviousness as follows:
The Examiner correct noted that Boemler et al. fails to disclose a common integrated circuit ... and looks to Tandon et al. to remedy this deficiency. ... [T]he analog image sensor of Tandon et al. comprises several discrete circuits 40, 42, 44, 50 for processing the output of the plurality of pixels to produce an analog output 52. The lateral voltage generator circuit provides the reset voltage for resetting the plurality of pixels.
The Examiner maintained the rejection in a Final Office Action, and the Applicant appealed.
The Appeal Brief argued the written description rejection by reproducing Figures 1 and 2 and the relied upon passages from the spec:
 The two column lines 16 and 20 are connected to a Read-Reset Amplifier (RRComp) circuit 22. The RRComp circuit 22 has two modes controlled by signals ReadMode and ResetMode. When a row of pixels is to be reset to a reference voltage VRT, these signals are ReadMode=0 and ResetMode=1 and the RRComp 22 functions as a unity gain buffer amplifier. When a row of pixel voltages is to be read out and converted into digital form, ReadMode=1 and ResetMode=0 and the RRComp 22 functions as an open loop amplifier or comparator.
(Emphasis in original.)
The Examiner elaborated on the Written Description rejection in the Answer, and in particular, explained his interpretation of the claim limitation at issue:
Appellant argues that the RRComp circuit 22 shown in Figs. 1 and 2 and functions in two modes creates support for the limitation "dual mode common integrated read-reset circuit". The examiner disagrees and notes that no where in the specification as originally filed is the limitation of an integrated circuit described. Further no description of RRComp 22 can be found that fits the definition of what an integrated circuit is. Citing the common understood definition from "The Authoritative Dictionary of IEEE Standards Terms, seventh edition published in 2000, an integrated circuit is "a combination of interconnected circuit elements inseparable associated on or within a continuous substrate" or "a combination of connected circuit elements (such as transistors, diodes, resistors, and capacitors) inseparably associated on or within a continuous substrate" or "a solid-state circuit consisting of interconnected active and passive semiconductor devices diffused into a single silicon chip". Nothing in the specification describes RRComp 22 as meeting anything of these definitions.
The Applicant did not file a Reply Brief.
The Board did not discuss claim construction, but moved on to quickly dismiss the Applicant's Written Description argument and affirm that rejection:
Appellant points to Figures 1 and 2 of Appellant’s drawings, reference numeral 22, the Read-Reset Amplifier (RRComp), to show that the circuit is integrated. App. Br. 8-9. ... However, we do not find that simply showing a circuit as a box equates to an integrated circuit.The Board also affirmed the obviousness rejection, citing to In re Larson (making components integral or separable is considered to be an obvious design choice) and KSR (predictable result of combination of known devices).
My two cents: As usual, this decision turns on claim construction. The Board often makes this point – even when neither the Applicant nor the Examiner acknowledge it. This decision did not discuss claim construction at all. Nonetheless, the Board's discussion of the Written Description rejection tells me that the Board interpreted "dual mode common integrated read-reset circuit" as requiring an "integrated circuit" as that term of art is understood by a POSITA.
The Board was right that putting a label on a box in a block diagram doesn't show that the inventor understood the box to be an "integrated circuit." It's true the application involved "integrated circuits" – the specification does mention CMOS and NMOS. Had the Applicant referred to that section of the spec, maybe the outcome would be different. Instead, the Applicant only discussed the sections of the spec which describe the dual mode aspect of the circuit. The Applicant appears to have completely ignored the Examiner's hints about claim construction in the Office Actions, and his explicit construction in the Answer.
What struck me about this case is this: I'm pretty sure the Applicant didn't intend to claim an "integrated circuit" as that term is understood by a POSITA. If so, the Applicant blew it by not arguing claim construction and/or amending once the Examiner's interpretation was clear.
It's true the application involved "integrated circuits" as that term is understood by a POSITA -- the specification does mention CMOS and NMOS. Even so, reading the argument the Applicant made to distinguish over the art, it seems clear to me that the Applicant used the adjective "integrated" in a different manner: to describe a single circuit which integrated two functions (buffer and comparator).
Once the Examiner's Answer explained that he was reading "integrated" to modify "circuit" and reading "integrated circuit" as a term of art, the Applicant should have dealt with this issue of claim construction. If the Applicant really wanted to hang his hat on this distinction (a circuit which integrated two functions), he should have either filed a Reply Brief with claim construction arguments, or should have pulled the case from appeal to amend the claim.
The limitation read "dual mode common integrated read-reset circuit." How persuasive would it be to argue that "integrated" refers to the dual mode aspect of the circuit and not the circuit as a whole? Under the "last antecedent" doctrine discussed in Finisar, only the adjective "read-reset" modifies "circuit." (Finisar Corp. v. The DirecTV Group, Inc., 523 F.3d 1323, 1335-36 (Fed. Cir. 2008).) On the other hand, this is prosecution and not litigation, and perhaps making this argument merely highlights that the claim could be interpreted either way, thus leading to an indefiniteness rejectiion under Ex parte Miyazaki.
How could the claim be amended to clarify? I think moving the adjective "integrated" so that the claim reads "integrated dual mode common read-reset circuit" is an improvement. Another option might be "single dual mode common read-reset circuit", although I suspect this would result in a § 112 rejection from some Examiners.
What about "integral" rather than "integrated"? "Integral" is commonly used in mechanical cases to mean (roughly) "one piece" – but we don't want to imply that the physical structure is one piece. The idea here is that two functions are combined into the read-reset circuit.
Finally, while I chose to focus on claim construction in this post, this type of distinction – circuit which integrates two functions – doesn't usually win the day, and it didn't win here. When the Applicant added the limitation discussed here, the Examiner switched from an anticipation to an obviousness rejection, pulling in a secondary reference to teach "supporting circuitry all on the same integrated circuit" and "an advantage to doing this is that the number of chips that need to be handled can be decreased." Not surprisingly, the Board affirmed the obviousness rejection, citing to In re Larson (making components integral or separable is considered to be an obvious design choice) and KSR (predictable result of combination of known devices).
So you won't be surprised to hear that after losing on appeal, the Applicant amended and the Examiner allowed the claim. The amendment removed "integrated" and added additional features related to the dual mode aspect:
a dual mode common integrated read-reset circuit, in each column, configured to
operate as a buffer in a first mode to apply the reset signal to the pixels while an output of the dual mode common read-reset circuit is coupled to the pixels, and to
operate as a comparator in a second mode to read pixel reset signals and pixel signals while an input of the dual mode common read-reset circuit is coupled to the pixels;