Board affirms obviousness when Applicant misunderstands Examiner's combination

Understanding the Examiner's position is key to advancing prosecution. Before appeal, it's best that the Applicant understands what the Examiner is saying, and that the Examiner understands what the Applicant is saying. Certainly a misunderstanding was at the root of the appeal of an obviousness rejection in Ex Parte Sudhardja. Sometimes the Examiner doesn't explain clearly, sometimes the Applicant just doesn't get it, and sometimes both forces are at work. What happened here?

Ex Parte Sudhardja
Appeal 2010-004119; Application No. 11/196,651; Tech. Center 2100
Decided  November 5, 2012

The application on appeal was directed to a "self-repairing" graphics processing unit (GPU) that included redundancy features. The application was a Continuation-In-Part. The parent application described redundant functional units in an integrated circuit; the CIP added GPU-specific details.



A representative independent claim on appeal – unchanged from the original filing – read:

     11. A self-reparable semiconductor including a graphics processing unit (GPU), comprising:
      M pixel processors that perform a first function, where M >= 1;
     at least one spare pixel processor that performs said first function and that is functionally interchangeable with said M pixel processors; and
     switching devices that communicate with said M pixel processors and said at least one spare pixel processor and that can selectively replace any of said M pixel processors with said spare pixel processor when said one of said M pixel processors is inoperable.

In the first Office Action, the Examiner rejected all claims as obvious over a combination of Adamovits and Gordon. According to the Examiner, Adamovits disclosed a telecommunications switch having redundancy features as claimed. The Examiner did acknowledge that the Adamovits device used network, rather than pixel, processors, then turned to Gordon (entitled "Pixel Processor"), which described implementing specific boolean functions on a pixel processor.

The Examiner explained the combination as follows:

Adamovits et al. does not teach the processor being a pixel processor. Gordon teaches of a pixel processor (Fig. 3, 303, col. 4 lines 60-67). It would have been obvious to modify Adamovits et al. sparing system by adding Gordon pixel processor.

As a rationale for combining, the Examiner asserted "[the combination] would provide redundant equipment to ensure acceptable and/or safe operation for the pixel processor."

In a first Response, the Applicant argued that the Examiner's combination did not produce the claimed invention. Since the Examiner specifically relied on "adding Gordon pixel processor" (emphasis added), the Applicant reasoned that the resulting combination included only "a single pixel processor" rather than M pixel processors as claimed. "The Examiner fails to provide any evidence in support of the allegation that modifying Adamovits et al. with the device of Gordon would result in multiple pixel processors" (emphasis added). 

In addition to attacking the combination itself, the Applicant also attacked the Examiner's rationale for combining, by highlighting differences in the types of devices: one related to switching network telecommunication data; and one graphics processing. Because of these differences, the Applicant concluded that "there is no suggestion to combine the teachings of Adamovits et al. and Gordon."

The Examiner provided more information in the Final Office Action.

Even though Adamovits et al. teach of a sparing system for processors, Adamovits et al. does not explicitly teach of a pixel processor. Gordon teaches of a pixel processor and [a POSITA] would conclude that it is obvious for Adamovits et al. to include pixel processors in the sparing configuration. Because Adamovits et al. taught of n pieces of equipment to at least one spare piece of equipment, examiner equate that as equal to applicant's M pixel processor where M> 1.

The Applicant appealed. The Appeal Brief reiterated that the Examiner's combination produced a sparing system with only a single pixel processor. The Applicant also elaborated on the no suggestion to combine argument (telecommunications data is unrelated to graphics processing) by noting that "adding a pixel processor [to a telecommunications switch] would provide no forseeable advantages."

The Examiner's Answer reiterated earlier positions, and also and re-stated the combination as: "combine the sparing system for n pieces of equipment of Adamovits with Gordon pixel processor for the sparing of pixel processors in a critical system." (Emphasis added.) Commenting on the unrelatedness of telecommunication switches and pixel processors, the Examiner noted that Adamovits specifically disclosed "the applicability [of sparing techniques] for critical equipment in a wide variety of applications and environments."

The Board affirmed the obviousness rejection, explaining that the Applicant had misunderstood the Examiner's combination:

While perhaps not described in the clearest manner, the Examiner's proposed rejection does not suggest only modifying one processor in Adamovits for a pixel processor as taught by Gordon. The Examiner proposes "combining the sparing system for n pieces of equipment of Adamovits with GOrdon pixel processors for the sparing of pixel processors in a critical system. (Emphasis in original.) Additionally, the Examiner finds that Adamovits teaches using one sparing piece of equipment for each n pieces of equipment in the system, suggesting that this spare equipment substitutes for each n pieces of equipment. 

The impact of these statements made by the Examiner signifies that the combination would substitute each of Adamovits sparing processors with a pixel processor as taught by Gordon, predictably yielding multiple spare pixel processors. Thus, looking at the rejection as a whole, combining Gordon with Adamovits, as proposed, also suggests substituting Adamovits' multiple processors with multiple pixel processors such that the substituted spare pixel processors are spare processors for M processors discussed in Adamovits.

Postscript: Upon losing this appeal, the Applicant filed a continuation with narrower claims and successfully prosecuted it to issuance.

My two cents: There are always two angles to attack in an obviousness rejection: Examiner's combination does not teach the claim elements; and rationale to combine. The Applicant here attacked both. The Applicant's does-not-teach argument was based on a faulty understanding of the Examiner's combination. Not sure how that happened, because I understood the combination asserted by the Examiner from the very first Office Action.

I was also spectacularly unpersuaded  – at first glance – by the Applicant's rationale-to-combine argument: "adding a pixel processor [to a telecommunications switch] would provide no forseeable advantages." Unpersuaded because my initial reaction was: "the advantage is the redundancy features."

But as I thought about it more, I started wondering if the Applicant was on to something. For one thing, the switch already had redundancy features, so that can't be the reason for using the pixel processors in the switch.

In fact, if you take the Applicant's argument a bit further, seems like you have a good argument for inoperable / unsuitable for intended purpose. Doesn't the telecommunications switch stop working when you replace its network processors with pixel processors? This isn't a case where a little re-work is all that is needed ... network processors have specific design features, useful for packet processing in a switch, that pixel processors don't.

What does seem to make sense is the inverse of the Examiner's combination. Take the redundancy features used in the telecommunications switch of the primary reference, and apply them to the graphics processor environment of the secondary reference.

Is this a different combination? I say it is. It's true there is case law that says the order of references doesn't matter (In re Mouttet, 686. F.3d 1322, 1333 (Fed. Cir. 2012, citing In re Bush, 296 F.2d 491, 496 (CCPA 1961)). But I'm not quibbling about which reference is labeled primary and which is labeled secondary. I'm talking about the fundamental question of how the references are combined to produce the claimed invention. 

This Applicant probably loses on the inverse combination as well. So you could say it doesn't matter. But stuff like this does matter.

It matters that the Examiner clearly explains his claim construction. It matters that the Examiner clearly explains how he's combining the references. It matters that the Examiner acknowledges that some limitations aren't present in the combination and he's relying on KSR's "creative inferences" to bridge the gap. And finally, it matters that the Examiner explains his rationale for combining.

Simply put, you can't effectively fight a rejection that you don't fully understand. Until the Federal Circuit rules that a prima facie case requires a complete explanation of the rejection, Applicants should work to extract this complete explanation from the Examiner over the course of prosecution.